1. Field of the Invention
The present invention relates to ESD (electrostatic discharge) protection devices, and more particularly to SCR type components that protect a signal line of a target circuit by shunting that line to ground or to a reference point or voltage; and even more particularly to stacking SCRs to protect a target circuit.
2. Background Information
Modern electronic circuitry is smaller, denser and more susceptible to electrostatic discharge events than circuitry of years past. For example, noise generated by the integrated circuits may inadvertently trigger a protection device, e.g. an SCR, and possibly damage the device. If the protective device is damaged, it may not protect the circuitry intended, and, if inadvertently triggered, it may render the circuitry inoperative. Typically when a SCR is triggered, power must be completely removed from the device to reset it back to an off state.
In prior art high voltage integrated circuitry (HVIC), a protective SCR may be triggered due to an ESD event, but when the ESD event ends and the regular power supply voltage returns, the SCR will remain on if the holding voltage is below the regular power supply voltage. In this case, the SCRs will hold down the power supply line making the target circuit inoperative. For example, if the HV power supply was +20V, a protective SCR may trigger at +40V, but the holding voltage may be +12.5V or so. Here the still on SCR's will compete with the power supply possibly damaging one or the other. In such a case the power to the SCR must be lowered below the holding voltage (or the power completely removed) to turn off the SCR. One approach to this problem may include stacking SCRs so that the holding voltage doubles. But, in such cases, the triggering voltage also doubles and may be too high. This dilemma has plagued the SCR circuitry for many years.
U.S. Pat. No. 6,671,153 approaches the above dilemma by stacking diodes in series with an SCR. The holding voltage is the sum of the holding voltage of the SCR plus the forward diode drops of the diodes. This may raise the holding voltage to a suitable level, but the triggering level may become too high requiring other techniques to lower to a useful level.
U.S. Pat No. 6,016,002 (′002) illustrates stacking two SCR's. However, the net effect is simple to stack two independent SCRs where the holding voltage doubles, but where the triggering voltage also doubles.
In more detail FIGS. 1 and 2, herein, are FIGS. 5 and 6 from the ′002 patent. Note that in FIG. 1, SCR 128 is a separate circuit that is stacked directly onto the independent circuit SCR 126. Other than the connection 124, the SCR's are separate and independent. Therefore, the characteristics of the SCR 128 simply add to the characteristics of SCR 126. Both the holding and the triggering voltages of the individual SCR's 128 and 126 add to each other.
It would be advantageous to stack two SCRs, where the holding voltage doubles, but where the triggering voltage remains that of a single SCR.